1. Field of the Invention
The present invention relates to a circuit simulation method, and more particularly, to a circuit simulation method for a circuit having a semiconductor resistor.
2. Description of Related Art
Along with miniaturization of semiconductor integrated circuits, an area of logic circuits is reduced, whereas, an area of analog circuits is not necessarily reduced. Therefore, reduction of the area of analog circuits has become an increasingly critical issue for cost reduction. A cause of an impediment to reducing the area of analog circuits is that it is difficult to reduce the area of resistors. Here, a terminal region of the resistor is connected to a wiring line through a plurality of contacts which are regularly arranged. A resistance of the terminal region of the resistor (hereinafter referred to as “terminal parasitic-resistance”) varies depending on the shape of the terminal region, the number and layout of contacts, or the like. Therefore, it is difficult to estimate the value of the resistance precisely.
When there is an estimation error of the terminal parasitic-resistance, it is necessary to enlarge a margin for the estimation error or to design the layout in which the estimation error is negligible. In each case, the circuit area increases. In particular, a resistance of contacts which are one of major components of the terminal parasitic-resistance increases at an accelerated rate along with the recent miniaturization. Therefore, the resistance of the terminal parasitic-resistance becomes large relative to a resistance of the main body of the resistor. Thus, the estimation error of the terminal parasitic-resistance has become an increasingly significant issue.
In general, to estimate a terminal parasitic-resistance, it is necessary to extract a complex parasitic-resistance net by using an LPE (Layout Parameter Extraction) tool after lay out design. Further, to shorten a circuit simulation time, a circuit reduction needs to be performed by a sequential hand calculation or a circuit reduction tool. However, such methods require time and effort or include estimation errors due to an LPE tool. For example, Japanese Unexamined Patent Application Publication No. 2008-204127 relates to a circuit reduction technique.